1. Technical Field
The present invention relates to a CMOS high voltage drive output buffer protection circuit and, more particularly, to a CMOS high voltage drive output buffer protection circuit formed in low voltage CMOS technology (e.g., 3.3 V) that is tolerant of high input voltages (e.g., 5 V).
2. Description of the Prior Art
In many areas of CMOS circuit design there are arrangements that include sections that run between 0-5 V and other sections that use a voltage supply range of only 0-3.3 V. There is often a need to provide a "buffer" circuit between these sections. Thus, there is a need to supply a circuit in standard low voltage CMOS technology (e.g., 3.3 V) that can drive a relative high voltage (e.g., 5 V) on its output. Additionally, many system configurations require a circuit that is "hot pluggable", meaning that the circuit will not draw any current from a bus that is at a high voltage, even when the circuit is not powered (i.e., when VDD is not present). Further, the circuit should be designed so that it is not "harmed" when exposed to relatively high voltages. In particular, if the gate oxide of a MOS transistor is subjected to too high a voltage, it will break down, causing gate-to-drain and/or gate-to-source shorts. Likewise, the drain-to-source junction of a MOS transistor will be degraded by hot carriers if it is subjected to too great a voltage. Thus, an MOS circuit that is subjected to voltages higher than the technology must be designed to work in such a way that the individual transistors in the circuit never see these higher voltages across their gate oxides or their source-to-drain junctions.
One problem with a low voltage technology CMOS buffer interfacing with a relatively high voltage is that the source of a P-channel output transistor is usually connected to the low voltage power supply VDD. If a voltage greater than VDD is applied to the drain of this device (where the drain is usually connected to the PAD of the buffer), it will forward bias the parasitic diode inherent in the P-channel device, since the N-tub backgate of the P-channel transistors is usually connected to VDD.
An exemplary prior art output buffer 10 capable of driving a relatively high voltage (5 V) in a low voltage technology (e.g., 3 V) is illustrated in FIG. 1. In particular, buffer circuit 10 is capable of driving 5 V without the voltage across any transistor rising above the "low voltage" level. As shown, buffer 10 comprises a resistor divider tree 12 formed of a plurality of N-tub resistors 14.sub.1 -14.sub.7 disposed between VSS (ground) and VDD5 (the 5 V power supply rail). Resistor divider tree 12 thus generates a plurality of different reference voltages, labeled VL1, VL2, VL3, VH1, VH2 and VH3 in FIG. 1. Resistors 14.sub.1 -14.sub.7 are sized such that VL3 is one-third of VDD5 and VH1 is two-thirds of VDD5. The voltages VL1 and VL2 are evenly divided between VSS and VL3, and the voltages VH2 and VH3 are evenly divided between VDD5 and VH1. Transistors 16-34 form a tapered inverter chain 36 whose output voltages are slowly shifted from the 0-VDD (i.e., 0-3 V) range to the VL3-VDD5 (i.e., 3.3-5 V) range. In particular, a first inverter formed by transistors 16 and 18 is biased between VDD and VSS, a second inverter (formed by transistors 20 and 22) is biased between VL1 and VH1, and so on, with the last inverter (formed by transistors 32 and 34) biased between VL3 and VDD5. The output from inverter chain 36, defined as node P in FIG. 1, is applied as the gate voltage to a P-channel transistor 38. By first shifting the voltage potentials associated with the power supplies, the voltage across the gate of transistor 38 will never be the full VDD5 potential, only the difference between VDD5 and VL3 (about 2 V). Transistor 40 acts as a source-follower clamp to keep node B from ever going above VDD-Vtn (where Vtn is defined as the N-channel transistor threshold voltage)--even when a full 5 V is applied to the PAD terminal. Similarly, transistor 42 clamps node C from ever going below VL3+Vtp (Vtp being a P-channel transistor threshold voltage)--even when the PAD terminal is held at zero.
While this circuit works well under normal conditions, it is not "hot-pluggable". "Hot pluggable" circuits must be able to tolerate a voltage on the PAD terminal even when the power supply (VDD5) is not present, without drawing any appreciable current from the device that is coupled to the PAD terminal. In the prior art circuit of FIG. 1, if VDD5 is not present, both VDD and VL3 can be at ground. Therefore, the gate oxides of transistors 40 and 42 will experience a 5 V stress if the PAD voltage reaches this level. Additionally, the parasitic diodes of transistors 38 and 42 (which are normally backgate biased to VDD5 as shown) can be easily turned "on" if VDD5 is not present, thereby drawing a large current from the device driving the voltage to PAD.
One known solution to the above "hot pluggable" problem is to utilize a relatively thick gate oxide for any devices that may be exposed to the relatively high voltages at their gate terminals and utilize a standard gate oxide for all remaining devices. In this case, transistors 38, 40 and 42 would require a thick oxide in order to be protected from PAD high voltages in the absence of VDD5. The use of two different gate oxide thicknesses is a very expensive technique that adds appreciable extra cost and process time to conventional CMOS processing technology.